1. Field of the Invention
The present invention relates to semiconductor memory devices and, more particularly, to a dynamic random access memory (DRAM) operable in a normal operation mode, a disturb test mode, and a self refresh mode.
2. Description of the Background Art
A semiconductor memory device called a DRAM, which stores data by accumulating charges in its capacitor, should be refreshed before the data is lost. Causes of data loss are disturb error attributable to a sub-threshold current of an access transistor, and pause error due to a leakage current in a PN junction of a storage node. Accordingly, some conventional DRAMs have a disturb test mode for conducting a disturb error accelerated test. In the disturb test mode, a predetermined data is written into a memory cell, a word line is frequently activated/inactivated repeatedly, and then it is examined whether or not the memory cell has retained the predetermined data within.
A semiconductor substrate, on which a memory cell and the others are formed, is usually biased with a negative substrate voltage so as to avoid latch up or the like. If this substrate voltage is set deeper, or the absolute value of the substrate voltage is made larger, disturb error is reduced while pause error is enhanced. Conversely, if the substrate voltage is set shallower, or the absolute value of the substrate voltage is made smaller, disturb error is enhanced whereas pause error is reduced. Therefore, in the disturb test mode, the substrate voltage is set shallow for further accelerating the disturb error.
Meanwhile, a DRAM having a self refresh mode is also available, which automatically performs refresh during standby. In the self refresh mode, the substrate voltage is set shallow so as to extend a refresh cycle during the mode to reduce power consumption. This is because pause error will have more adverse effects on data erasure than disturb error during standby, when a memory cell is not accessed.
In Japanese Patent Laying-Open No. 8-329674, for example, a substrate voltage generating circuit for setting the substrate voltage shallow in a self refresh mode is disclosed. The substrate voltage generating circuit includes: a first voltage generating circuit for generating a deep substrate voltage in a normal operation mode; a first level sensor for determining the level of a substrate voltage generated by the first voltage generating circuit; a second voltage generating circuit for generating a shallow substrate voltage during standby; and a second level sensor for determining the level of a substrate voltage generated by the second voltage generating circuit.
When manufacturing a DRAM having both of the above-described disturb test mode and self refresh mode, providing separate circuits for generating a shallow substrate voltage, one for a disturb test mode and the other for a self refresh mode, will result in an increased layout area penalty.
Further, when such a DRAM enters a disturb test mode or a self refresh mode from a normal operation mode, the substrate voltage should be made shallower, so that a problem will arise that the transition from the normal operation mode to the disturb test mode or the self refresh mode will take relatively long time.
Similarly, when the same DRAM returns from the disturb test mode or the self refresh mode to the normal operation mode, the substrate voltage must be brought back to a deeper level, which will again lead to the problem as described above that transition time from the disturb test mode or the self refresh mode to the normal operation mode will become long.